Intel 815 - Manual (Page 111)

I/O Subsystem
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Intel
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815 Chipset Platform Design Guide 111
10 I/O Subsystem
This chapter provides guidelines for connecting and routing the IDE, AC’97, USB, I/O APIC,
SMBus, PCI, LPC/FWH, and RTC subsystems.
10.1 IDE Interface
This section contains guidelines for connecting and routing the ICH IDE interface. The ICH has
two independent IDE channels. This section provides guidelines for IDE connector cabling and
motherboard design, including component and resistor placement and signal termination for both
IDE channels. The ICH has integrated the series resistors that typically have been required on the
IDE data signals (PDD[15:0] and SDD[15:0]) running to the two ATA connectors. Intel does not
anticipate requiring additional series termination, but OEMs should verify the motherboard signal
integrity via simulation. Additional external 0
Ω
resistors can be incorporated into the design to
address possible noise issues on the motherboard. The additional resistor layout increases
flexibility by providing future stuffing options.
The IDE interface can be routed with 5-mil traces on 5-mil spaces, and it should be less than
8 inches long (from ICH to IDE connector). Additionally, the shortest IDE signal (on a given IDE
channel) must be less than 1 inch shorter than the longest IDE signal (on the channel).
10.1.1 Cabling and Motherboard Requirements
•
Length of Cable: Each IDE cable must be equal to or less than 18 .
•
Cable Capacitance: Less than 30 pF.
•
Placement: A maximum of 6 inches between drive connectors on the cable. If a single drive
is placed on the cable, it should be placed at the end of the cable. If a second drive is placed
on the same cable, it should be placed on the connector next closest to the end of the cable
(6 inches away from the end of the cable).
•
Grounding: Provide a direct low-impedance chassis path between the motherboard ground
and hard disk drives.
•
Ultra ATA/66: Ultra ATA/66 requires the use of an 80-conductor cable.
•
ICH Placement: The ICH must be placed at most 8 inches from the ATA connector(s).
•
Termination Resistors: There is no need for series termination resistors on the data and
control signals, since series termination is integrated into these signal lines on the ICH.
•
Capacitance: The capacitance of each pin of the IDE connector on the host should be less
than 25 pF when the cables are disconnected from the host.
•
IDE Absent: If no IDE is implemented with the ICH, the input signals (xDREQ and
xIORDY) can be grounded and the output signals can be left as no connects.