Intel 815 - Manual (Page 95)

AGP/Display Cache Design Guidelines
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Intel
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815 Chipset Platform Design Guide 95
7.5.2 VREF Generation for AGP 2.0 (2X and 4X)
VREF generation for AGP 2.0 is different, depending on the AGP card type used. The 3.3V AGP
cards generate VREF locally. That is, they have a resistor divider on the card that divides VDDQ
down to VREF
(see Figure 47). To account for potential differences between VDDQ and GND at
the GMCH and graphics controller, 1.5V cards use source-generated VREF. That is, the VREF
signal is generated at the graphics controller and sent to the GMCH, and another VREF is
generated at the GMCH and sent to the graphics controller (see Figure 47).
Both the graphics controller and the GMCH must generate VREF and distribute it through the
connector (1.5V add-in cards only). The following two pins defined on the AGP 2.0 universal
connector allow this VREF passing:
•
VREFGC : VREF from the graphics controller to the chipset
•
VREFCG : VREF from the chipset to the graphics controller
To preserve the common mode relationship between the VREF and data signals, the routing of the
two VREF signals must be matched in length to the strobe lines, within 0.5 inch on the
motherboard and within 0.25 inch on the add-in card.
The voltage divider networks consist of AC and DC elements, as shown in Figure 47.
The VREF divider network should be placed as close as practical to the AGP interface, to get the
benefit of the common-mode power supply effects. However, the trace spacing around the VREF
signals must be a minimum of 25 mils to reduce cross-talk and maintain signal integrity.
During 3.3V AGP 2.0 operation, VREF must be 0.4 VDDQ. However, during 1.5V AGP 2.0
operation, VREF must be 0.5 VDDQ. This requires a flexible voltage divider for VREF. Various
methods of accomplishing this exist, and one such example is shown in Figure 47.