Intel 815 - Manual (Page 45)

System Bus Design Guidelines
R
Intel
®
815 Chipset Platform Design Guide 45
Table 7. Example T
FLT_MAX
Calculations for 133 MHz Bus
1
Driver Receiver Clk Period
2
TCO_MAX TSU_MIN ClkSKEW ClkJITTER MADJ Recommended
TFLT_MAX
Processor GMCH 7.50 3.25 2.65 0.20 0.25 0.40 1.1
GMCH Processor 7.50 4.1 1.20 0.20 0.25 0.40 1.35
NOTES:
1. All times in nanoseconds
2. BCLK period = 7.50 ns at 133.33 MHz
Table 8. Example T
FLT_MIN
Calculations (Frequency Independent)
Driver Receiver THOLD ClkSKEW TCO_MIN Recommended
TFLT_MIN
Processor GMCH 0.10 0.20 0.40 0.10
GMCH Processor 1.00 0.20 1.05 0.15
NOTES: All times in nanoseconds
The flight times in Table 7 include margin to account for the following phenomena that Intel
observed when multiple bits are switching simultaneously. These multi-bit effects can adversely
affect the flight time and signal quality and sometimes are not accounted for during simulation.
Accordingly, the maximum flight times depend on the baseboard design, and additional adjustment
factors or margins are recommended.
•
SSO push-out or pull-in
•
Rising or falling edge rate degradation at the receiver caused by inductance in the current
return path, requiring extrapolation that causes additional delay
•
Cross-talk on the PCB and inside the package which can cause variation in the signals
Additional effects exist that may not necessarily be covered by the multi-bit adjustment factor
and should be budgeted as appropriate to the baseboard design. These effects are included as M
ADJ
in the example calculations in Table 7. Examples include:
•
The effective board propagation constant (SEFF), which is a function of:

Dielectric constant (
ε
r) of the PCB material

Type of trace connecting the components (stripline or microstrip)

Length of the trace and the load of the components on the trace. Note that the board
propagation constant multiplied by the trace length is a component of the flight time, but
not necessarily equal to the flight time.