System memory design guidelines, System memory routing guidelines, Figure 34. system memory routing guidelines – Intel 815 User Manual

Page 69

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System Memory Design Guidelines

R

Intel

®

815 Chipset Platform Design Guide

69

6

System Memory Design
Guidelines

6.1

System Memory Routing Guidelines

Ground plane reference all system memory signals. To provide a good current return path and
limit noise on the system memory signals, the signals should be ground referenced from the
GMCH to the DIMM connectors and from DIMM connector-to-DIMM connector. If ground
referencing is not possible, system memory signals should be, at a minimum, referenced to a single
plane. If single plane referencing is not possible, stitching capacitors should be added no more
than 200 mils from the signal via field. System memory signals may via to the backside of the PCB
under the GMCH without a stitching capacitor as long as the trace on the topside of the PCB is
less than 200 mils.

Note: Intel recommends that a parallel plate capacitor between VCC3.3SUS and GND be added to

account for the current return path discontinuity (See decoupling section). Use one 0.01

µ

F X7R

capacitor per every five system memory signals that switch plane references. No more than two
vias are allowed on any system memory signal.

If a group of system memory signals must to change layers, a via field should be created and a
decoupling capacitor should be added at the end of the via field. Do not route signals in the middle
of a via field; this causes noise to be generated on the current return path of these signals and can
lead to issues on these signals (see Figure 34). The traces shown are on layer 1 only. The figure
shows signals that are changing layer and two signals that are not changing layer.

Note: The two signals around the via field create a keepout zone where no signals that do not change

layer should be routed.

Figure 34. System Memory Routing Guidelines

Do not route any signal in

the middle of the via field

that do not change layers

Add (1) 0.01 uf capacitor

X7R (5) signals that via

Stagger vias in via field to avoid

power/ground plane cut off because

of the antipad on the internal layers

sys-mem-route

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