System bus design guidelines, System bus routing guidelines, Initial timing analysis – Intel 815 User Manual
Page 43: 5system bus design guidelines, 1 system bus routing guidelines, 1 initial timing analysis
System Bus Design Guidelines
R
Intel
®
815 Chipset Platform Design Guide
43
5
System Bus Design Guidelines
The Pentium III processor delivers higher performance by integrating the Level-2 cache into the
processor and running it at the processor’s core speed. The Pentium III processor runs at higher
core and system bus speeds than previous-generation Intel
®
IA-32 processors while maintaining
hardware and software compatibility with earlier Pentium III processors. The new Flip Chip-Pin
Grid Array 2 (FC-PGA2) package technology enables compatibility with previous Flip Chip-Pin
Grid Array (FC-PGA) packages using the PGA370 socket.
This section presents the considerations for designs capable of using the Intel 815 chipset platform
with the full range of Pentium III processors using the PGA370 socket.
5.1
System Bus Routing Guidelines
The following layout guide supports designs using Pentium III processor (CPUID=068xh) /
Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processors with the Intel
815 chipset platform for use with the universal socket 370. The solution covers system bus speeds
of 66/100/133 MHz for the Pentium III processor (CPUID=068xh) / Celeron processor
(CPUID=068xh), and future 0.13 micron socket 370 processors. All processors must also be
configured to 56
Ω
on-die termination.
5.1.1
Initial Timing Analysis
Table 6 lists the AGTL/AGTL+ component timings of the processors and GMCH defined at the
pins.
Note: These timings are for reference only. Obtain each processor’s specifications from the respective
processor datasheet and the chipset values from the appropriate Intel 815 chipset datasheet.