Intel 815 - Manual (Page 99)

AGP/Display Cache Design Guidelines
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Intel
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815 Chipset Platform Design Guide 99
7.8 AGP / Display Cache Shared Interface
As described earlier, the AGP and display cache interfaces of the Intel 815 chipset platform are
multiplexed or shared. In other words, the same component pins (balls) are used for both
interfaces, although obviously only one interface can be supported at any given time. As a result,
almost all display cache interface signals are mapped onto the new AGP interface. The Intel 815
chipset platform can be configured in either AGP mode or Graphics mode. In the AGP mode, the
interface supports a full AGP 4X interface. In the Graphics mode, the interface becomes a display
cache interface similar to the Intel
810E chipset. Note, however, that in the Graphics mode, the
display cache is optional. There do not have to be any SDRAM devices connected to the interface.
The only dedicated display cache signals are OCLK and RCLK, which need not connect directly
to the SDRAM devices. These are not mapped onto existing AGP signals.
7.8.1 GPA Card Considerations
To support the fullest flexibility, the display cache exists on an add-in card (Graphics Performance
Accelerator, or GPA) that complies with the AGP connector form factor. If the motherboard
designer follows the flexible routing guidelines for the AGP interface detailed in previous sections,
the customer can choose to populate the AGP slot in a system based on the Intel 815 chipset
platform with either an AGP graphics card, with a GPA card to enable the highest-possible internal
graphics performance, or with nothing to get the lowest-cost internal graphics solution. Some of
the GPA/ Intel 815 chipset platform for use with the universal socket 370 interfacing implications
are listed below. For a complete description of the GPA card design, refer to the Graphics
Performance Accelerator Card Specification available from Intel.
•
A strap is required to determine which frequency to select for display cache operation. This is
the L_FSEL pin of the GMCH. The GPA card will pull this signal up or down, as appropriate
to communicate to the appropriate operating frequency to the Intel 815 chipset platform. The
platform will sample this pin on the deasserting edge of reset.
•
Since current SDRAM technology is always 3.3V rather than the 1.5V option also supported
by AGP, the GPA card should set the TYPEDET# signal correctly to indicate that it requires a
3.3V power supply. Furthermore, the GPA card should have only the 3.3V key and not the
1.5V key, thereby preventing it from being inserted into a 1.5V-only connector.
•
The pad buffers on the chip will be the normal AGP buffers and will work for both interfaces.
•
In internal graphics mode, the AGPREF signal, which is required for the AGP mode, should
remain functional as a reference voltage for sampling 3.3V LMD inputs. The voltage level on
AGPREF should remain exactly the same as in the AGP mode, as opposed to VCC/2 used for
previous products.
7.8.1.1 AGP and GPA Mechanical Considerations
The GPA card will be designed with a notch on the PCB to go around the AGP universal retention
mechanism. To guarantee that the GPA card will meet all shock and vibration requirements of the
system, the AGP universal retention mechanism will be required on all AGP sockets that are to
support a GPA card.