Intel 815 - Manual (Page 124)

I/O Subsystem
R
124 Intel
®
815 Chipset Platform Design Guide
10.6 SMBus
The Alert on LAN signals can be used as:
•
Alert on LAN signals: 4.7 k
Ω
pull-up resistors to 3.3VSB are required.
•
GPIOs: Pull-up resistors to 3.3VSB and the signals must be allowed to change states on
power-up. (For example, on power-up the ICH drives heartbeat messages until the BIOS
programs these signals as GPIOs.) The values of the pull-up resistors depend on the loading
on the GPIO signal.
•
Not Used: 4.7 k
Ω
pull-up resistors to 3.3VSB are required.
If the SMBus is used only for the three SPD EEPROMs (one on each RIMM), both signals should
be pulled up with a 4.7 k
Ω
resistor to 3.3V.
10.7 PCI
The ICH provides a PCI bus interface that is compliant with the PCI Local Bus Specification,
Revision 2.2. The implementation is optimized for high-performance data streaming when the ICH
is acting as either the target or the initiator on the PCI bus. For more information on the PCI bus
interface, refer to the PCI Local Bus Specification, Revision 2.2.
The ICH supports 6 PCI Bus masters by providing 6 REQ#/GNT# pairs. In addition, the ICH
supports 2 PC/PCI REQ#/GNT# pairs, one of which is multiplexed with a PCI REQ#/GNT# pair.
Based on simulations performed by Intel, a maximum of 4 PCI slots should be connected to the
ICH. This limit is due to timing and loading considerations established during simulations. If a
system designer wants 5 PCI slots connected to the ICH, then the designer’s company should
perform its own simulations to verify a proper design.
Figure 64. PCI Bus Layout Example for Four PCI Connectors
IO_subsys_PCI_layout
ICH