Intel 815 - Manual (Page 148)

Power Delivery
R
148 Intel
®
815 Chipset Platform Design Guide
12.4 1.85V/3.3V Power Sequencing
This section shows the timings among various signals during different power state transitions.
Figure 73. G3-S0 Transition
Clocks invalid Clocks valid
t17
t16 t15
t14
t13
t12
t10
t11
t9
t8
t7
t6
t5
t4
t3 t2
t1
Vcc3.3sus
RSMRST#
SLP_S3#
SLP_S5#
SUS_STAT#
Vcc3.3core
CPUSLP#
PWROK
Clocks
PCIRST#
Cycle 1 from GMCH
Cycle 1 from ICH
Cycle 2 from GMCH
Cycle 2 from ICH
STPCLK#
Freq straps
CPURST#
pwr_G3-S0_trans