Intel 815 - Manual (Page 153)

Power Delivery
R
Intel
®
815 Chipset Platform Design Guide 153
output buffers that are normally disabled, and the ICH may unexpectedly drive these signals if the
3.3V supply is active while the 1.85V supply is not.
Figure 77 shows an example power-on sequencing circuit that ensures the 2V Rule is obeyed. This
circuit uses a NPN (Q2) and PNP (Q1) transistor to ensure the 1.85V supply tracks the 3.3V
supply. The NPN transistor controls the current through PNP from the 3.3V supply into the 1.85V
power plane by varying the voltage at the base of the PNP transistor. By connecting the emitter of
the NPN transistor to the 1.85V plane, current will not flow from the 3.3V supply into 1.85V plane
when the 1.85V plane reaches 1.85V.
Figure 77. Example 1.85V/3.3V Power Sequencing Circuit
Q1
PNP
Q2
NPN
220
220
470
+3.3V +1.8V
When analyzing systems that may be “marginally compliant” to the 2V Rule, pay close attention to
the behavior of the ICH’s RSMRST# and PWROK signals, since these signals control internal
isolation logic between the various power planes:
•
RSMRST# controls isolation between the RTC well and the Resume wells.
•
PWROK controls isolation between the Resume wells and Main wells
If one of these signals goes high while one of its associated power planes is active and the other is
not, a leakage path will exist between the active and inactive power wells. This could result in
high, possibly damaging, internal currents.