Intel 815 - Manual (Page 40)

Universal Socket 370 Design
R
40 Intel
®
815 Chipset Platform Design Guide
4.2.10 GTLREF Topology and Layout
In a platform supporting the future 0.13 micron socket 370 processors, the voltage requirements
for GTLREF are different for the processor and the chipset. The GTLREF on the processor is
specified to be 2/3 * VTT, while the GTLREF on the chipset is 0.7 * VTT. This difference
requires that separate resistor sites be added to the layout to split the GTLREF sources. In a
universal motherboard design, a Pentium III processor (CPUID=068xh) and Celeron processor
(CPUID=068xh) will be unaffected by the difference in GTLREF. The recommended GTLREF
circuit topology is shown in Figure 16.
Note: If an A-2 stepping of the GMCH is used with the universal motherboard design, the GTLREF for
the GMCH should be set at 2/3 * VTT. This requires changing the 63.4
Ω
, 1% resistor on the
GMCH side to 75
Ω
, 1%.
Figure 16. GTLREF Circuit Topology
gtlref_circuit
V TT
63.4 Ω 75 Ω
150 Ω 150 Ω
Processor GMCH
GTLREF Layout and Routing Guidelines
•
Place all resistor sites for GTLREF generation close to the GMCH.
•
Route GTLREF with as wide a trace as possible.
•
Use one 0.1
µ
F decoupling capacitor for every two GTLREF pins at the processor (four
capacitors total). Place as close as possible (within 500 mils) to the Socket 370 GTLREF pins.
•
Use one 0.1
µ
F decoupling capacitor for each of the two GTLREF pins at the GMCH
(two capacitors total). Place as close as possible to the GMCH GTLREF balls.
Given the higher GTLREF level for the GMCH, a debug test hook should be added for validation
purposes. The debug test hook should be placed on the processor signal ADS# and consists of
laying down the site for a 56
Ω
pull-up to VTT. The resistor site should be located within 150 mils
of the GMCH, and placed as close to the ADS# signal trace as possible.