Vddq/vcc1_85 power sequencing, 85v/3.3v power sequencing, Figure 76. vddq power sequencing circuit – Intel 815 User Manual

Page 152: 1 vddq/vcc1_85 power sequencing

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Power Delivery

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152

Intel

®

815 Chipset Platform Design Guide

12.4.1

VDDQ/VCC1_85 Power Sequencing

For the consideration of long term component reliability, the following power sequence is strongly
recommended while the AGP interface of the GMCH is running at 3.3V. If the AGP interface is
running at 1.5V, the following power sequence recommendation is no longer applicable. The
power sequence recommendation is:

During the power-up sequence, the 1.85V must ramp up to 1.0V before 3.3V ramps above
2.2V

During the power-down sequence, the 1.85V cannot ramp below 1.0V before 3.3V ramps
below 2.2V

The same power sequence recommendation also applies to the entrance and exit of S3 state

System designers need to be aware of this requirement while designing the voltage regulators and
selecting the power supply. An example VDDQ power sequencing circuit is shown in Figure 76.

Figure 76. VDDQ Power Sequencing Circuit

SHDN

VIN

GND

FB

IPOS

INEG

GATE

COMP

3.3V

1.85V

vddq_pwr_seq

1 K

1 K

1 K

12.4.2

1.85V/3.3V Power Sequencing

The ICH has two pairs of associated 1.85V and 3.3V supplies. These are {Vcc1_8, Vcc3_3} and
{VccSus1_8, VccSus3_3}. These pairs are assumed to power up and power down together. The
difference between the two associated supplies must never be greater than 2.0V.
The 1.85V
supply may come up before the 3.3V supply without violating this rule (though this is generally
not practical in a desktop environment, since the 1.85V supply is typically derived from the 3.3V
supply by means of a linear regulator).

One serious consequence of violation of the 2V Rule, is electrical overstress of oxide layers,
resulting in component damage.

The majority of the ICH I/O buffers are driven by the 3.3V supplies, but are controlled by logic
that is powered by the 1.85V supplies. Thus, another consequence of faulty power sequencing
arises if the 3.3V supply comes up first. In this case the I/O buffers will be in an undefined state
until the 1.85V logic is powered up. Some signals that are defined as “Input-only” actually have

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