Intel 815 - Manual (Page 144)

Power Delivery
R
144 Intel
®
815 Chipset Platform Design Guide
Refer to Section 12.4.1 for more information on the power ramp sequence requirement between
3.3V and 1.85V. System designers need to be aware of this requirement while designing the
voltage regulators and selecting the power supply. For further details on the voltage sequencing
requirements, refer to the Intel
®
815 Chipset Family: 82815 Graphics and Memory Controller
Hub (GMCH) For Use With Universal Socket 370 Datasheet.
Note: This regulator is required in ALL designs (unless the design does not support 1.5V AGP, and
therefore does not support 4X AGP).
3.3VSB
The 3.3VSB plane powers the I/O buffers in the resume well of the ICH and the PCI 3.3Vaux
suspend power pins. The 3.3Vaux requirement state that during suspend, the system must deliver
375 mA to each wake-enabled card and 20 mA to each non wake-enabled card. During full-power
operation, the system must be able to supply 375 mA to each card. Therefore, the total current
requirement is:
•
Full-power Operation: 375 mA * number of PCI slots
•
Suspend Operation: 375+20 mA * (number of PCI slots – 1)
In addition to the PCI 3.3Vaux, the ICH suspend well power requirements must be considered as
shown in Figure 71.
Note: This regulator is required in all designs.
1.85VSB
The 1.85VSB plane powers the logic to the resume well of the ICH. This should not be used for
VCMOS.
12.1 Thermal Design Power
Thermal Design Power (TDP) is defined as the estimated maximum possible expected power
generated in a component by a realistic application. It is based on extrapolations in both hardware
and software technology over the life of the product. It does not represent the expected power
generated by a power virus.
The TDP for the GMCH component is 5.1 W.
12.1.1 Pull-Up and Pull-Down Resistor Values
The pull-up and pull-down values are system dependent. The appropriate value for a system can be
determined from an AC/DC analysis of the pull-up voltage used, the current drive capability of the
output driver, the input leakage currents of all devices on the signal net, the pull-up voltage
tolerance, the pull-up/pull-down resistor tolerance, the input high-voltage/low-voltage
specifications, the input timing specifications (RC rise time), etc. Analysis should be performed to
determine the minimum/maximum values usable on an individual signal. Engineering judgment
should be used to determine the optimal value. This determination can include cost concerns,
commonality considerations, manufacturing issues, specifications, and other considerations.