Intel 815 - Manual (Page 125)

I/O Subsystem
R
Intel
®
815 Chipset Platform Design Guide 125
10.8 LPC/FWH
10.8.1 In-Circuit FWH Programming
All cycles destined for the FWH will appear on the PCI. The ICH hub interface to the PCI bridge
puts all processor boot cycles out on the PCI (before sending them out on the FWH interface). If
the ICH is set for subtractive decode, these boot cycles can be accepted by a positive decode agent
on PCI. This enables booting from a PCI card that positively decodes these memory cycles. To
boot from a PCI card, it is necessary to keep the ICH in subtractive decode mode. If a PCI boot
card is inserted and the ICH is programmed for positive decode, there will be two devices
positively decoding the same cycle. In systems with the Intel
® 82380AB (ISA bridge), it also is
necessary to keep the NOGO signal asserted when booting from a PCI ROM. Note that it is not
possible to boot from a ROM behind the Intel 82380AB. After booting from the PCI card, one
potentially could program the FWH in circuit and program the ICH CMOS.
10.8.2 FWH V
PP
Design Guidelines
The V
PP
pin on the FWH is used for programming the flash cells. The FWH supports a V
PP
of
3.3V or 12V. If V
PP
is 12V, the flash cells will program about 50% faster than at 3.3V. However,
the FWH only supports 12 V V
PP
for 80 hours. The 12 V V
PP
would be useful in a programmer
environment, if it typically is an event that occurs very infrequently (much fewer than 80 hours).
The V
PP
pin must be tied to 3.3V on the motherboard.
10.9 RTC
The ICH contains a real-time clock (RTC) with 256 bytes of battery-backed SRAM. This internal
RTC module provides two key functions: keeping the date and time and storing system data in its
RAM when the system is powered down. This section explains the recommended hookup for the
RTC circuit for the ICH.
Note: This circuit is not the same as the circuit used for the PIIX4.