Intel 815 - Manual (Page 164)

System Design Checklist
R
164 Intel
®
815 Chipset Platform Design Guide
Checklist Items Recommendations
PDD[15:0], PDIOW#,
PDIOR#, PDREQ,
PDDACK#, PIORDY,
PDA[2:0], PDCS1#,
PDCS3#, SDD[15:0],
SDIOW#, SDIOR#,
SDREQ, SDDACK#,
SIORDY, SDA[2:0],
SDCS1#, SDCS3#, IRQ14,
IRQ15 • No external series termination resistors on those signals with integrated
series resistors.
PCIRST# • The PCIRST# signal should be buffered to the IDE connectors.
No floating inputs (including
bi-directional signals): • Unused core well inputs should be tied to a valid logic level (either pulled
up to 3.3V or pulled down to ground). Unused resume well inputs must
be either pulled up to 3.3VSB or pulled down to ground. Ensure all
unconnected signals are OUTPUTS ONLY!
PDD[15:0], SDD[15:0] • PDD7 and SDD7 need a 10 k Ω (approximate) pull-down resistor. No
other pull-ups/pull-downs are required. Refer to ATA ATAPI-4
specification.
PIORDY, SDIORDY • Use approximately 1 k Ω pull-up resistor to 5V.
PDDREQ, SDDREQ • Use approximately 5.6 k Ω pull-down resistor to ground.
IRQ14, IRQ15 • Need 8.2 k Ω (approximate) pull-up resistor to 5V.
HL11 • No pull-up resistor required. A test point or no stuff resistor is needed to
be able to drive the ICH into a NAND tree mode for testing purposes.
VCCRTC • No clear CMOS jumper on VCCRTC. Use a jumper on RTCRST# or a
GPI, or use a safe-mode strapping for clear CMOS.
SMBus:
SMBCLK
SMBDATA
• The value of the SMBus pull-ups should reflect the number of loads on
the bus. For most implementations with 4–5 loads, 4.7 k Ω resistors are
recommended. OEMs should conduct simulation to determine exact
resistor value.
APICD[0:1], APICCLK • If the APIC is used: 150 Ω (approximate) pull-ups on APICD[0:1] and
connect APICCLK to the clock generator.
• If the APIC is not used: The APICCLK can either be tied to GND or
connected to the clock generator, but not left floating.
GPI[8:13] • Ensure all wake events are routed through these inputs. These are the
only GPIs that can be used as ACPI-compliant wake events because
they are the only GPI signals in the resume well that have associated
status bits in the GPE1_STS register.
HL_COMP • RCOMP Method: Tie the COMP pin to a 40 Ω 1% or 2% (or 39 Ω 1%)
pull-up resistor to 1.85V via a 10-mil wide, very short(-0.5 inch) trace
(targeted for a nominal trace impedance of 40
Ω )
5V_REF • Refer to Section 12.4.3 for implementation of the voltage sequencing
circuit.
SERIRQ • Pull-up through 8.2 k Ω resistor (approximate) to 3.3V
SLP_S3#, SLP_S5# • No pull-ups required. These signals are always driven by the ICH.
CLK66 • Use 18 pF tuning capacitor as close as possible to ICH.
GPIO27/ALERTCLK
GPIO28/ALERTDATA • Add a 10 k Ω pull-up resistor to 3VSB (3 V standby) on both of these
signals.
PCI_GNT# • No external pull-ups are required on PCI_GNT# signals. However, if
external pull-ups are implemented, they must be pulled up to 3.3V.