Intel 815 - Manual (Page 25)

General Design Considerations
R
Intel
®
815 Chipset Platform Design Guide 25
2 General Design Considerations
This document provides motherboard layout and routing guidelines for systems based on the Intel
815 chipset platform for use with the Universal Socket 370. The document does not discuss the
functional aspects of any bus or the layout guidelines for an add-in device.
If the guidelines listed in this document are not followed, it is very important that thorough signal
integrity and timing simulations be completed for each design. Even when the guidelines are
followed, it is recommended that critical signals be simulated to ensure proper signal integrity and
flight time. Any deviation from these guidelines should be simulated.
The trace impedance typically noted (i.e., 60
Ω
± 15%) is the “nominal” trace impedance for a
5-mil-wide trace. That is, it is the impedance of the trace when not subjected to the fields created
by changing current in neighboring traces. When calculating flight times, it is important to
consider the minimum and maximum impedance of a trace, based on the switching of neighboring
traces. Using wider spaces between the traces can minimize this trace-to-trace coupling. In
addition, these wider spaces reduce the settling time.
Coupling between two traces is a function of the coupled length, the distance separating the traces,
the signal edge rate, and the degree of mutual capacitance and inductance. To minimize the effects
of trace-to-trace coupling, the routing guidelines documented in this section should be followed.
Additionally, the routing guidelines in this document are created using a PCB stack-up similar to
that described in the following section.
2.1 Nominal Board Stackup
The Intel 815 chipset platform requires a board stack-up yielding a target impedance of
60
Ω
± 15%, with a 5-mil nominal trace width. Figure 3 shows an example stack-up that achieves
this. It is a 4-layer printed circuit board (PCB) construction using 53%-resin, FR4 material.
Figure 3. Board Construction Example for 60
Ω Ω Ω Ω
Nominal Stackup
board_4.5mil_stackup
~48-mil Core
Component-side layer 1: ½ oz. Cu
Power plane layer 2: 1 oz. Cu
4.5-mil prepreg
Ground layer 3: 1 oz. Cu
Solder-side layer 4: ½ oz. Cu
4.5-mil prepreg
Total thickness:
62 mils