Intel 815 - Manual (Page 42)

Universal Socket 370 Design
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42 Intel
®
815 Chipset Platform Design Guide
4.3.2 Gating of PWROK to ICH
With power being gated to the Intel CK-815 by the signal VTTPWRGD12, it is important that the
clocks to the ICH are stable before the power supply asserts PWROK to the ICH. As the clocking
power gating circuitry relies on the 12V supply, there is no guarantee that these conditions will be
met. This is why an estimated minimum time delay of 20 ms must be added after power is
connected to the Intel CK-815 to give the clock driver sufficient time to stabilize. This time delay
will gate the power supply’s assertion of PWROK to the ICH. After the time delay, the power
supply can safely assert PWROK to the ICH, with the ICH subsequently taking the GMCH out of
reset. Refer to Figure 18 for an example implementation.
Figure 18. PWROK Gating Circuit For ICH
43 k Ω
PW ROK
ICH_PW ROK_GATING
Note:
Delay 20 m s after VDD
on CK-815 is powered
VDD on CK-815 VCC3_3
ICH_PW ROK
8.2 k Ω
1.0 µ F
NOTE: The diode is included so that repeated pressing of the reset or power button does not cause the
capacitor to build up enough charge to circumvent the 20 ms delay.