Intel 815 - Manual (Page 146)

Power Delivery
R
146 Intel
®
815 Chipset Platform Design Guide
12.3 Power Management Signals
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A power button is required by the ACPI specification.
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PWRBTN# is connected to the front panel on/off power button. The ICH integrates 16 ms
debouncing logic on this pin.
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AC power loss circuitry has been integrated into the ICH to detect power failure.
•
It is recommended that the ATXPWROK signal from the power supply connector be routed
through a Schmitt trigger to square-off and maintain its signal integrity. It should not be
connected directly to logic on the board.
•
PWROK logic from the power supply connector can be powered from the core voltage
supply.
•
RSMRST# logic should be powered by a standby supply, while making sure that the input to
the ICH is at the 3V level. The RSMST# signal requires a minimum time delay of 1 ms from
the rising edge of the standby power supply voltage. A Schmitt trigger circuit is recommended
to drive the RSMRST# signal. To provide the required rise time, the 1-ms delay should be
placed before the Schmitt trigger circuit. The reference design implements a 20 ms delay at
the input of the Schmitt trigger to ensure that the Schmitt trigger inverters have sufficiently
powered up before switching the input. Also ensure that voltage on RSMRST# does not
exceed VCC(RTC).
•
It is recommended that 3.3V logic be used to drive RSMRST# to alleviate rise time problems
when using a resistor divider from VCC5.
•
The PWROK signal to the chipset is a 3V signal.
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The core well power valid to PWROK asserted at the chipset is a minimum of 1 ms.
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PWROK to the chipset must be deasserted after RSMRST#.
•
PWRGOOD signal to processor is driven with an open-collector buffer pulled up to 2.5V,
using a 330
Ω
resistor.
•
RI# can be connected to the serial port if this feature is used. To implement ring indicate as a
wake event, the RS232 transceiver driving the RI# signal must be powered when the ICH
suspend well is powered. This can be achieved with a serial port transceiver powered from the
standby well that implements a shutdown feature.
•
SLP_S3# from the ICH must be inverted and then connected to PSON of the power supply
connector to control the state of the core well during sleep states.
•
For an ATX power supply, when PSON is low, the core wells are turned on. When PSON is
high, the core wells from the power supply are turned off.