Altera PCI Compiler - Manual (Page 143)

Altera Corporation User Guide Version 11.1 3–69
October 2011
Functional Description
Figure 3–17 shows the same transaction as in Figure 3–16 with the PCI
bus master inserting a wait state. The 64-bit extension signals are not
applicable to the pci_mt32 and pci_t32 functions. The PCI bus master
inserts a wait state by deasserting the irdyn signal in clock cycle 7. The
effect of this wait state on the local side is shown in clock cycle 8 as the
MegaCore function deasserts lt_ackn and as a result lt_dxfrn is also
deasserted. This prevents data from being transferred to the local side in
clock cycle 8 because the internal pipeline of the function does not have
valid data.
Figure 3–17. Burst Memory Write Target Transaction with PCI Master Wait State
Note to Figure 3–17 :
(1) This signal is not applicable to the pci_mt32 or pci_t32 MegaCore functions.
ad[31..0]
(1) ad[63..32]
cben[3..0]
(1) cben[7..4]
par
(1) par64
framen
(1) req64n
irdyn
devseln
(1) ack64n
trdyn
stopn
lt_framen
l_adro[31..0]
l_cmdo[3..0]
lt_rdyn
lt_ackn
l_dato[31..0]
lt_dxfrn
(1) l_ldat_ackn
(1) l_hdat_ackn
clk
(1) l_dato[63..32]
l_beno[3..0]
(1) l_beno[7..4]
lt_tsr[11..0]
Adr
7
Adr-PAR
Adr
7
BE0_L
BE0_H
000 381
D0_L
D0_H
D0_L
D0-L-PAR
D0-H-PAR
BE0_L
BE0_H
000 781 381
D1_L D2_L D3_L
D1_L D2_L D3_L
D1_H D2_H D3_H
D1-L-PAR
D1-H-PAR
D2-L-PAR
D2-H-PAR
D3-L-PAR
D3-H-PAR
D0_H
2 3 4 5 6 7 9 10 12 8 11 1 13 14
D1_H D2_H D3_H
781
BE1_L BE2_L BE3_L
BE1_H BE2_H BE3_H
BE1_L BE2_L BE3_L
BE1_H BE2_H BE3_H