Altera PCI Compiler - Manual (Page 182)

3–108 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Master Mode Operation
Master Write Transactions
This section describes the behavior of the PCI MegaCore functions in the
following types of master write transactions:
■ Memory write
■ I/O and configuration write
Memory Write Transactions
The PCI MegaCore functions support the following types of matched bus
width and mismatched bus width memory write transactions in master
mode:
■ Burst memory write
■ 32-bit single-cycle memory write
■ 64-bit single-cycle memory write
■ Mismatched bus width memory write
1 Mismatched bus-width transactions are 32-bit PCI transactions
performed by the pci_mt64 MegaCore function.
For each type of transaction, the following sequence of events is the same:
1. The local side asserts lm_req32n (and lm_req64n in the case of a
64-bit transaction) to request a transaction. Consequently, the PCI
side asserts reqn to request mastership of the bus from the PCI
arbiter.
2. When the PCI bus arbiter grants mastership by asserting the gntn
signal, the local side asserts lm_adr_ackn to acknowledge the
transaction’s address and command. During the same clock cycle
when lm_adr_ackn is asserted, the local side provides the address
on the l_adi bus and the command on l_cbeni[3..0]. At the
same time, the pci_mt64 or pci_mt32 function turns on the
drivers for framen (and req64n, in the case of a 64-bit transaction.)