Altera PCI Compiler - Manual (Page 271)

Altera Corporation User Guide Version 11.1 7–3
October 2011
Functional Description
Figure 7–1. Generic PCI-Avalon Bridge Block Diagram
Avalon-MM Ports
The Avalon bridge is comprised of up to four (depending on device
operating mode) predefined ports to communicate with the interconnect.
This section discusses the four Avalon-MM ports:
■ Prefetchable Avalon-MM master
■ Non-Prefetchable Avalon-MM master
■ PCI bus access slave
■ Control register access Avalon-MM slave
Prefetchable Avalon-MM Master
The prefetchable Avalon-MM master port provides a high bandwidth
PCI memory request access to Avalon-MM slave peripherals. This master
port is capable of generating Avalon-MM burst requests for PCI requests
that hit a prefetchable base address register (BAR). You should only
connect prefetchable Avalon-MM slaves to this port, typically RAM or
ROM memory devices.
PCI-Avalon Bridge
PCI
MegaCore
Function
PCI
Target
Controller
System
Interconnect
Fabric
Control
Register
Access Avalon
Slave
Control
Status
Registers
PCI
Prefetchable
Bridge
Logic
PCI
Non-
Prefetchable
Bridge Logic
PCI
Bus
PCI
Master
Controller
Master
Bridge
Logic
PCI Bus
Access
Slave
PCI Bus
Arbiter
Prefetchable
Avalon
Master
Non-
Prefetchable
Avalon
Master