Altera PCI Compiler - Manual (Page 307)

Altera Corporation User Guide Version 11.1 7–39
October 2011
Functional Description
● PCI target, configuration writes are the only requests accepted,
which are never delayed. These requests are handled directly by
the PCI core.
■ DRC—Delayed read completion
■ DWC—Delayed write completion. These are never passed through to
the core in either direction. Incoming configuration writes are never
delayed. Delayed write completion status is not passed back at all.
The following sections describe the special ordering logic and adherence
to the PCI-SIG specifications for each direction through the PCI-Avalon
bridge.
Ordering of Avalon-to-PCI Operations
Read and write requests in the Avalon-to-PCI direction are handled in a
first-in, first-out order through the Avalon-to-PCI command/write data
buffer. As read commands are read out of the Avalon-to-PCI
command/write data buffer they can be placed in the Avalon-to-PCI
bypassable read buffer, which allows them to be passed by writes.
To preserve the producer/consumer ordering model, delayed read
completions (for reads handled as a PCI target) cannot pass writes in the
PCI-to-Avalon direction. To preserve this ordering relationship, the valid
flag for data returned from the interconnect is passed through the
Avalon-to-PCI command/write data buffer. Because the buffer is
handled in a first-in, first-out order, the read response data valid flag will
not be indicated on the PCI side until all previous Avalon-to-PCI write
commands are finished.
Figure 7–11 shows the ordering logic used in the Avalon-to-PCI direction.