Altera PCI Compiler - Manual (Page 224)

4–14 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Testbench Specifications
in the PCI transactions as required by your application. You can also
create new procedures or tasks that are not currently implemented in the
target transactor by using the existing procedures or tasks as an example.
Bus Monitor (monitor)
The bus monitor displays PCI transactions and information messages to
the simulator's console window and in the log.txt file when an event
occurs on the PCI bus. The bus monitor also sends the PCI transaction
status to the master transactor. The bus monitor reports the following
messages:
■ Target retry
■ Target abort
■ Target terminated with disconnect-A (target terminated with data)
■ Target terminated with disconnect-B (target terminated without
data)
■ Master abort
■ Target not responding
The bus monitor reports the target termination messages depending on
the state of the trdyn, devseln, and stopn signals during a transaction.
The bus monitor reports a master abort if devseln is not asserted within
four clock cycles from the start of a PCI transaction. It reports that the
target is not responding if trdyn is not asserted within 16 clock cycles
from the start of the PCI transaction. You can modify the bus monitor to
include additional PCI protocol checks as needed by your application.
Clock Generator (clk_gen)
The clock generator, or clk_gen, module generates the PCI clock for the
Altera PCI testbench. This module generates a 66-Mhz clock if the
pciclk_66Mhz_enable
parameter is set to true in the PCI testbench
top-level file, otherwise, it generates a 33-Mhz clock. The default value of
pciclk_66Mhz_enable
is true.