I/o write transactions – Altera PCI Compiler User Manual
Page 149
Altera Corporation
User Guide Version 11.1
3–75
October 2011
Functional Description
I/O Write Transactions
I/O write transactions by definition are 32 bits.
shows a
sample I/O write transaction. The sequence of events is the same as 32-
bit single-cycle memory write transactions. The main distinction between
the two transactions is the command on the lt_cmdo[3..0] bus.
1
The PCI MegaCore functions do not ensure that the combination
of the ad[1..0] and cben[3..0] signals is valid during the
address phase of an I/O transaction. Local side logic should
implement this functionality if performing I/O transactions.
Refer to the PCI Local Bus Specification, Revision 3.0 for more
information on handling invalid combinations of these signals.
Figure 3–21. I/O Write Transaction
ad[31..0]
cben[3..0]
par
framen
irdyn
devseln
(1) ack64n
trdyn
stopn
lt_framen
l_adro[31..0]
l_cmdo[3..0]
lt_rdyn
lt_ackn
l_dato[31..0]
lt_dxfrn
clk
l_beno[3..0]
lt_tsr[11..0]
Adr
3
Adr-PAR
Adr
3
BE0_L
000
102
D0_L
D0_L
D0-L-PAR
BE0_L
000
1
2
3
4
5
6
7
8
9
10
11
502