Altera PCI Compiler - Manual (Page 150)

3–76 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Target Mode Operation
Configuration Write Transactions
Configuration write transactions are 32 bits. Configuration cycles are
automatically handled by the PCI MegaCore functions and do not require
local side actions.
Figure 3–22 shows a typical configuration write
transaction. The configuration write transaction is similar to a 32-bit
single-cycle transaction, except for the following:
■ During the address phase, idsel must be asserted in a configuration
transaction
■ Because the configuration write does not require local side actions,
the PCI MegaCore function asserts trdyn independent from the
lt_rdyn
signal
1 The local side cannot retry, disconnect, or abort configuration
cycles.
Figure 3–22. 32-Bit Configuration Write Transaction
ad[31..0]
cben[3..0]
par
framen
idsel
irdyn
devseln
trdyn
stopn
clk
lt_tsr[11..0]
Adr
B
Adr-PAR
BE0_L
D0_L
D0-L-PAR
1 2 3 4 5 6 7 8 9 10 11
000 100 000 500