Altera PCI Compiler - Manual (Page 264)

6–14 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
PCI Configuration
Hardwired PCI Address —The hardwired PCI address setting allows you
to hardwire the PCI BAR so the system software does not configure it at
run time. To use this option, select YES and enter a hardwired BAR value.
1 The Hardwired PCI Address option is generally useful for the
PCI Host-Bridge Device mode and embedded applications,
because system designers have complete control over system
configuration. This option is not recommended for other
applications.
Manual Setting of the BAR Size & Avalon Base Address
The number of high-order bits (starting from the most significant bit) in
the BAR that the PCI device implements as read/write bits determines
the size of address to which it will respond. A 32-bit BAR can be
implemented to support a contiguous memory size that is a power of 2
from 1 KByte to 2 GBytes. If you select a base address size of 1 MByte
(using a 32-bit BAR), the PCI-Avalon bridge will implement the 12 most
significant bits (bits 31-20) of the base address registers as read/write and
hardwire the remaining bits to 0 (except for the least significant 4 bits
because they have special use).
Figure 6–2 shows a pictorial view of the
PCI BAR address range.
Figure 6–2. Pictorial View of the 32-Bit PCI BAR
Start =
End =
0xFE60_0000
0xFE6F_FFFF
[BASE] 0...0
[BASE] 1...1
PCI Memory Address Range
BAR Range
0xFFFF_FFFF
0x0000_0000