Altera PCI Compiler - Manual (Page 327)

Altera Corporation User Guide Version 11.1 7–59
October 2011
Functional Description
Table 7–27 describes the current PCI status register. This register shows
the current status of the PCI rstn and int[a:d]n lines.
Table 7–27. Current PCI Status Register – Address 0x306C
Bit Name
Access
Mode
Description
2:0 Reserved N/A
3 MASTER_ENABLE_CURRENT_VALUE RO Current value of the PCI command register
master enable bit (command register bit 2).
0 – Not enabled to master transactions on the PCI
bus.
1 – Enabled to master transactions on the PCI
bus.
This bit will always be set to 0 when the bridge is
operating in the PCI target mode.
4 Reserved N/A
5 A2P_WRITE_IN_PROGRESS RO 0 – There are no Avalon-to-PCI writes pending in
the PCI-Avalon bridge module
1 – There is at least one Avalon-to-PCI write
pending in the PCI-Avalon bridge module
Due to clock synchronization delays, there will be
a slight delay between an Avalon-to-PCI write
entering the bridge module and this bit being set.
The delay could be up to five of the slowest clock
cycles.
If an application is concerned about the
completion of configuration writes on the target
bus, the configuration write can be issued by itself
and then this bit can be read to confirm when the
write is no longer pending. The
ERR_PCI_WRITE_FAILURE bit should be
checked to determine if there was an error on the
write.
6 INTAN_CURRENT_VALUE RO Current value of the PCI intan signal.
0 – PCI int A is being signaled.
1 – PCI int A is not being signaled.
This bit is only implemented when the bridge is
operating in the PCI Host-Bridge Device mode.
31:7 Reserved N/A