Altera PCI Compiler - Manual (Page 190)

3–116 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Master Mode Operation
Figure 3–41 shows the same transaction as in Figure 3–38 but with the PCI
bus target inserting a wait state. This figure applies to both the pci_mt64
and pci_mt32 MegaCore functions, excluding the 64-bit extension
signals as noted for pci_mt32. The PCI target inserts a wait state by
deasserting trdyn in clock cycle 9. Consequently, on the following clock
cycle (clock cycle 10), the pci_mt64 and pci_mt32 functions deassert
the lm_ackn and lm_dxfrn signals on the local side. Data transfer is
suspended on the PCI side in clock cycle 9 and on the local side in clock
cycle 10. Also, because lm_lastn is asserted and lm_rdyn is deasserted
in clock cycle 11, the lm_ackn and lm_dxfrn signals remain deasserted
after clock cycle 12.