Table 3–5 – Altera PCI Compiler User Manual
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3–16
User Guide Version 11.1
Altera Corporation
PCI Compiler
October 2011
PCI Bus Signals
shows definitions for the PCI status register bits.
Local Address, Data, Command, & Byte Enable Signals
summarizes the PCI local interface signals for the address, data,
command, and byte enable signals.
Table 3–5. PCI Status Register Output Bus (stat_reg[6..0]) Bit Definition
Bit Number
Bit Name
Description
0
perr_rep
Parity error reported. Status register bit 8.
1
tabort_sig
Target abort signaled. Status register bit 11.
2
tabort_rcvd
Target abort received. Status register bit 12.
3
mabort_rcvd
Master abort received. Status register bit 13.
4
serr_sig
Signaled system error. Status register bit 14.
5
perr_det
Parity error detected. Status register bit 15.
6
int_stat
Interrupt status. Status register bit 3.
Note to
(1)
This signal is added for compliance with the PCI Local Bus Specification, Revision 3.0.