Altera Quartus II Settings File - Manual (Page 176)

SYNTH_GATED_CLOCK_CONVERSION
Automatically converts gated clocks in the design to use clock enable pins if clock enable pins are not used
in the original design. Clock gating logic can contain AND, OR, MUX, and NOT gates. Turning on this
option may increase memory use and overall run time. You must use the TimeQuest Timing Analyzer for
timing analysis, and you must define all base clocks in Synopsys Design Constraints (SDC) format.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION -entity <entity
name> <value>
set_instance_assignment -name SYNTH_GATED_CLOCK_CONVERSION -to <to> -entity
<entity name> <value>
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION <value>
Default Value
Off
Example
set_global_assignment -name synth_gated_clock_conversion on
set_instance_assignment -name synth_gated_clock_conversion on -to foo
176 SYNTH_GATED_CLOCK_CONVERSION
MNL-Q21005
2015.05.04
Altera Corporation Quartus Settings File Reference Manual
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