Altera Quartus II Settings File - Manual (Page 96)

FORCE_SYNCH_CLEAR
Forces the Compiler to utilize synchronous clear signals in normal mode logic cells. Turning on this
option helps to reduce the total number of logic cells used in the design, but might negatively impact the
fitting since synchronous control signals are shared by all the logic cells in a LAB.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name FORCE_SYNCH_CLEAR <value>
set_global_assignment -name FORCE_SYNCH_CLEAR -entity <entity name> <value>
set_instance_assignment -name FORCE_SYNCH_CLEAR -to <to> -entity <entity
name> <value>
Default Value
Off
Example
set_global_assignment -name force_synch_clear on
set_instance_assignment -name force_synch_clear on -to foo
See Also
Allow Synchronous Control Signals
96 FORCE_SYNCH_CLEAR
MNL-Q21005
2015.05.04
Altera Corporation Quartus Settings File Reference Manual
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