Altera Quartus II Settings File - Manual (Page 625)

MATCH_PLL_COMPENSATION_CLOCK
Allows you to specify a PLL output clock feeding a clock network as a compensation target for a PLL in
NORMAL or SOURCE_SYNCHRONOUS mode. This configures the PLL to match its feedback path to
the target's clock network. This option is ignored if it is applied to anything other than a PLL output clock.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports Fitter wildcards.
This assignment is included in the Fitter report.
Syntax
set_instance_assignment -name MATCH_PLL_COMPENSATION_CLOCK -to <to> -entity
<entity name> <value>
MNL-Q21005
2015.05.04
MATCH_PLL_COMPENSATION_CLOCK 625
Quartus Settings File Reference Manual Altera Corporation
Send Feedback