Altera Quartus II Settings File - Manual (Page 334)

SIGNALRACE_RULE_CLK_PORT_RACE
Direct Design Assistant to check race condition between clock port and any other port of the same
register.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_global_assignment -name SIGNALRACE_RULE_CLK_PORT_RACE <value>
334 SIGNALRACE_RULE_CLK_PORT_RACE
MNL-Q21005
2015.05.04
Altera Corporation Quartus Settings File Reference Manual
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