Altera Quartus II Settings File - Manual (Page 517)

DUAL_PURPOSE_CLOCK_PIN_DELAY
Specifies the propagation delay from a dual-purpose clock pin to its fan-out destinations that are routed
on the global clock network. Legal integer values range from 0 through 63 for Cyclone and Cyclone II
device families and from 0 through 11 for Cyclone III, where 0 is the setting with the least delay and 63 is
the setting with the most delay. This is an advanced option that should be used only after you have
compiled a project, checked the I/O timing, and determined that the timing is unsatisfactory. For detailed
information on how to use this option, refer to the data sheet for the device family. This option is ignored
if it is applied to anything other than an input or bidirectional pin, or if the pin is user assigned to a non-
dual-purpose clock pin location.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports Fitter wildcards.
Syntax
set_instance_assignment -name DUAL_PURPOSE_CLOCK_PIN_DELAY -to <to> -entity
<entity name> <value>
MNL-Q21005
2015.05.04
DUAL_PURPOSE_CLOCK_PIN_DELAY 517
Quartus Settings File Reference Manual Altera Corporation
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