Altera Quartus II Settings File - Manual (Page 666)

OUTPUT_PIN_LOAD
Specifies the capacitive load, in picofarads (pF), on output pins for each I/O standard. Note: These settings
affect FPGA pins only. To specify board trace, termination, and capacitive load parameters for use with
Advanced I/O Timing, use the Board Trace Model tab. Capacitive loading is ignored if applied to
anything other than an output or bidirectional pin, or if Advanced I/O Timing is enabled.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
INTEGER_RANGE
0, 10000
Notes
This assignment is copied to any duplicated nodes.
Syntax
set_instance_assignment -name OUTPUT_PIN_LOAD -to <to> -entity <entity
name> <value>
set_global_assignment -name OUTPUT_PIN_LOAD -section_id <section
identifier> <value>
666 OUTPUT_PIN_LOAD
MNL-Q21005
2015.05.04
Altera Corporation Quartus Settings File Reference Manual
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