Altera PHYLite - Manual (Page 16)

Related Information
• Device Pin-Out File
For specific DQS group numbers refer to the specific device Pin-Out file
Reference Clock
The reference clock must be placed on a clock input in one of the banks used by the interface. If the
reference clock is used for multiple interfaces (consisting of a combination of EMIF and Altera PHYLite
for Parallel Interfaces IPs), it can be placed in any bank used by any of the interfaces, but the banks for all
interfaces must be contiguous.
Constraining Multiple Altera PHYLite for Parallel Interfaces to One I/O Bank
To constrain groups from separate Altera PHYLite for Parallel Interfaces IP core instances into the same
I/O bank, the instances must share the same reference clock and reset sources, the same external memory
frequencies and the same voltage settings.
Dynamic Reconfiguration
If you are using the dynamic reconfiguration feature, all interfaces of the Arria 10 External Memory
Interfaces and Altera PHYLite for Parallel Interfaces IP cores in the same I/O column must share the
reset
signal. Multiple IP cores requiring Avalon core access require daisy chain connectivity.
Related Information
Daisy Chain on page 20
Describes the daisy chain connectivity
Timing
The Quartus II software version 14.1 generates the required timing constraints to analyze the timing of
the Altera PHYLite for Parallel Interfaces IP core on the Arria 10 device.
16 Reference Clock
ug_altera_phylite
2015.01.16
Altera Corporation Altera PHYLite for Parallel Interfaces IP Core User Guide
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