Altera PHYLite - Manual (Page 5)

Interface
Figure 4: Top-Level Interface
This figure shows the top-level diagram of the Altera PHYLite for Parallel Interfaces IP core interface.
PLL
I/O Lane
I/O Lane
Tile Control
I/O Lane
I/O Lane
VCO/Interpolator
phy_clk
phy_clk_phs
core_clk_out
data_in/out/io
data_in/out/io
Data to/from Core
Group
ref_clk
Reference Clock
Core Clock PHY Clock
ExternalClock
Legend
The Altera PHYLite for Parallel Interfaces IP core consists of the following interfaces:
• Clocks and Reset
• Core Data and Control (broken down into input and output paths)
• I/O (broken down into input and output paths)
• Avalon Configuration Bus
Related Information
• Output Path on page 5
For more information about the output path
• Input Path on page 8
For more information about the input path
• Signals on page 37
For more information about core data, control, and I/O interfaces signals
Output Path
The output path consists of a FIFO and an interpolator.
ug_altera_phylite
2015.01.16
Interface 5
Altera PHYLite for Parallel Interfaces IP Core User Guide Altera Corporation
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