Altera PHYLite - Manual (Page 57)

Figure 32: Group 1 settings (Output type for Addr/Cmd)
Figure 33: Group 2 settings (Input type for the Ready signal)
The following figure shows the RTL viewer for a NAND Flash simple design based on the Altera PHYLite
for Parallel Interfaces IP core implementation above.
ug_altera_phylite
2015.01.16
Implementation using the Altera PHYLite for Parallel Interfaces IP Core 57
Altera PHYLite for Parallel Interfaces IP Core User Guide Altera Corporation
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