Altera PHYLite - Manual (Page 43)

Generating Example Design
You can generate a example design by clicking Example Design in the IP Parameter Editor.
The software generates a user defined directory in which the example design files reside.
The <instance>_example_design directory contains two TCL scripts:
•
- make_qii_design.tcl
•
- make_sim_design.tcl
Generating Quartus Example Design
The
make_qii_design.tcl
generates a synthesizable example design along with a Quartus project, ready
for compilation.
To generate synthesizable example design, run the following script at the end of IP generation:
quartus_sh -t make_qii_design.tcl
To specify an exact device to use, run the following script:
quartus_sh -t make_qii_design.tcl [device_name]
This script generates a qii directory containing a project called ed_synth.qpf. You can open and compile
this project with the Quartus II software.
Generating Simulation Example Design
The
make_sim_design.tcl
generates a simulation example design along with tool-specific scripts to
compile and elaborate the necessary files.
To generate a simulation example design for a Verilog or a mixed-language simulator, run the following
script at the end of IP generation:
quartus_sh -t make_sim_design.tcl VERILOG
To generate simulation example design for a VHDL-only simulator, run the following script:
quartus_sh -t make_sim_design.tcl VHDL
This script generates a sim directory containing one subdirectory for each supported simulation tools.
Each subdirectory contains the specific scripts to run simulation with the corresponding tool.
The simulation example design provides a generic example of the core and I/O connectivity for your IP
configuration. Functionally, the simulation will iterate over each group in your configured IP and
performs basic reads/writes to an associated agent (one per group) in the testbench. A simple one group
Altera PHYLite instantiation in the testbench is used for basic address and command outputs to the agent.
A side bus between the
sim_ctrl
and the agents is used to check that the reads and writes are valid.
ug_altera_phylite
2015.01.16
Generating Example Design 43
Altera PHYLite for Parallel Interfaces IP Core User Guide Altera Corporation
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