Internal fpga path timing violation, Dynamic reconfiguration, Rtl connectivity – Altera PHYLite User Manual
Page 20: Daisy chain
Related Information
on page 20
For more information about using the dynamic reconfiguration feature to calibrate the I/O path
Internal FPGA Path Timing Violation
If timing violations are reported at the internal FPGA paths (such as
<instance_name>_usr_clk
or
<instance_name>_phy_clk_*
), consider the following guidelines:
If setup time violation is reported, lower the clock rate of the user logic from full-rate to half-rate, or from
half-rate to quarter-rate. This reduces the frequency requirement of the IP core-to-core data transfer.
If hold time violation is observed, overconstrain the hold uncertainty in the .sdc to force the Fitter to fix
the hold time violation. Under normal circumstances, the Fitter should already attempt to avoid hold time
violation. It is possible that the Fitter may think adding more delay to avoid hold time at the fast timing
corner may cause setup time violation at the slow corner.
Dynamic Reconfiguration
Due to the asynchronous nature of the PHY, you must perform calibration to achieve timing closure at a
high frequency. At a high level, calibration involves reconfiguring input and output delays in the PHY to
align data and strobes. Enabling dynamic reconfiguration in the Altera PHYLite for Parallel Interfaces IP
core provides allows you to modify these delays using an Avalon-MM interface.
RTL Connectivity
When generating the Altera PHYLite for Parallel Interfaces IP core with the dynamic reconfiguration
feature enabled, the Altera PHYLite for Parallel Interfaces IP core exposes the Avalon-MM master and
Avalon-MM slave interfaces. If the generated IP core is the only Altera PHYLite for Parallel Interfaces IP
core (with dynamic reconfiguration) or Arria 10 External Memory Interfaces IP core in the I/O column,
then only the slave interface needs to be used with a master in the core. Otherwise, both interfaces must be
connected as described in the following section.
Daisy Chain
The I/O column provides a single physical Avalon-MM interface. All IP cores in the I/O column that
require Avalon access from the core use the same physical Avalon-MM interface. The system level RTL
for the column reflects this resource limitation by using a daisy chain to connect all dynamically reconfig‐
urable IP cores in an I/O column.
The Altera PHYLite for Parallel Interfaces IP core exposes a 28-bit Avalon-MM address, where the top 4-
bits are the ID of the interface to be addressed in the daisy chain. These bits are only required for the daisy
chain arbitration in RTL simulation, so they are synthesized away during compilation. If only one
interface is addressed from the core, it is sufficient to tie these bits off to the interface’s ID.
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Internal FPGA Path Timing Violation
ug_altera_phylite
2015.01.16
Altera Corporation
Altera PHYLite for Parallel Interfaces IP Core User Guide