Getting started with the cpri v6.0 ip core, Getting started with the cpri v6.0 ip core -1 – Altera CPRI v6.0 MegaCore Function User Manual
Page 12
Getting Started with the CPRI v6.0 IP Core
2
2014.08.18
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Explains how to install, parameterize, and simulate the Altera CPRI v6.0 IP core.
on page 2-2
The CPRI v6.0 IP core is an extended IP core which is not included with the Quartus II release. This
section provides a general overview of the Altera extended IP core installation process to help you quickly
get started with any Altera extended IP core.
Specifying IP Core Parameters and Options
on page 2-2
After you install and integrate the extended IP core in the ACDS release, the CPRI v6.0 IP core supports
the standard customization and generation process. This IP core does not generate a testbench or example
design simultaneously with generation of the IP core. Instead, you must use the Example Design button in
the CPRI v6.0 parameter editor to generate the testbench. This IP core is not supported in Qsys.
Files Generated for Altera IP Cores
on page 2-3
The Quartus software generates the following IP core output file structure.
The CPRI v6.0 parameter editor provides the parameters you can set to configure the CPRI v6.0 IP core
and simulation testbench.
Integrating Your IP Core in Your Design: Required External Blocks
You must connect your CPRI v6.0 IP core to some additional required design components. Your design
can compile without some of these connections and logical blocks, but it will not function correctly in
hardware unless all of them are present and connected in your design.
on page 2-16
The Quartus II software supports RTL- and gate-level design simulation of Altera IP cores in supported
EDA simulators. Simulation involves setting up your simulator working environment, compiling
simulation model libraries, and running your simulation.
on page 2-17
Altera provides a demonstration testbench with the CPRI v6.0 IP core.
To run the Altera CPRI v6.0 IP core demonstration testbench, follow these steps.
Related Information
Refer to the "Integrating IP Cores" section of this Quartus II Handbook chapter for more information
about generating an Altera IP core and integrating it in your Quartus II project.
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