Altera CPRI v6.0 MegaCore Function - Manual (Page 24)

Drive the clean-up PLL with the CPRI v6.0 IP core
xcvr_recovered_clk
output clock, and connect the
cleaned up output to the external TX PLL input reference clock port.
Related Information
CPRI v6.0 IP Core Clocking Structure on page 3-3
Adding the External TX PLL
The CPRI v6.0 IP core requires that you generate and connect an external TX PLL IP core. The
transceiver PLL IP core configures the TX PLL in the transceiver in hardware, but you must generate the
transceiver PLL IP core separately from the CPRI v6.0 IP core in software. If you do not generate and
connect the transceiver PLL IP core, the CPRI v6.0 IP core does not compile.
You can use the IP Catalog to generate the external PLL IP core that configures a TX PLL on the device. In
the IP Catalog, select an Altera IP core that configures an appropriate PLL on your target device.
In the Stratix V TX PLL parameter editor, you must set the following parameter values:
• Enable PLL reconfiguration: Turn on if you turned on Enable auto-rate negotiation in the CPRI v6.0
parameter editor. Otherwise, turn off.
• Number of TX PLL reference clocks: 1.
• PLL feedback path: Set to internal.
• PLL type: Select a type that supports the CPRI line bit rate you specified in the CPRI v6.0 parameter
editor.
• PLL base data rate: Set to the CPRI line bit rate you specified in the CPRI v6.0 parameter editor.
• Selected reference clock source: Set to 0.
For your Arria 10 design, you can select Arria 10 Transceiver ATX PLL, Arria 10 Transceiver CMU
PLL, or Arria 10 FPLL in the IP Catalog. In the parameter editor for the TX PLL IP core you select, you
must set the following parameter values:
• PLL output frequency to one half the per-lane data rate of the IP core variation. The transceiver
performs dual edge clocking, using both the rising and falling edges of the input clock from the PLL.
Therefore, this PLL output frequency setting drives the transceiver with the correct clock for the
Interlaken lanes.
• PLL reference clock frequency to a frequency at which you can drive the TX PLL input reference
clock. You must drive the external PLL reference clock input signal at the frequency you specify for
this parameter.
Arria 10 devices and the Quartus II software support multiple options for configuring an Arria 10 TX
PLL. Depending on the TX PLL IP core you select and the configuration options you prefer, you have a
wide range of choices in parameterizing the external TX PLL for an Arria 10 variation.
You must connect the external TX PLL signals and the CPRI v6.0 IP core transceiver TX PLL interface
signals according to the following rules:
• Connect the
xcvr_ext_pll_clk
input signal of the CPRI v6.0 IP core to the
pll_clkout
or
tx_serial_clk
output signal of the external PLL IP core.
• If your CPRI v6.0 IP core is an RE slave, drive the input signal of the external PLL IP core with the
output of the external cleanup PLL.
UG-01156
2014.08.18
Adding the External TX PLL 2-13
Getting Started with the CPRI v6.0 IP Core Altera Corporation
Send Feedback