Cpri v6.0 ip core registers, Cpri v6.0 ip core registers -1 – Altera CPRI v6.0 MegaCore Function User Manual
Page 90
CPRI v6.0 IP Core Registers
5
2015.02.16
UG-01156
The CPRI v6.0 IP core internal registers are accessible using the CPU interface, an Avalon-MM interface
which conforms to the Avalon Interface Specifications.
All of these registers are 32 bits wide and the addresses are shown as hexadecimal values. The registers can
be accessed only on a 32-bit (4-byte) basis. The addressing for the registers therefore increments by units
of 4.
Write access to a Reserved or undefined location has no effect. Read accesses to a Reserved or undefined
location return an undefined result.
Table 5-1: Register Access Codes
Lists the access codes used to describe the type of register bits.
Code
Description
RW
Read / write
RO
Read only
RC
Read to clear
UR0
Reserved —undefined result on read, no effect on write
Table 5-2: Control and Status Register Map
Offset
Register Name
Function
Location of Additional Information
0x00
INTR
Interrupt Control and
Status
0x04
L1_STATUS
Layer 1 Status
3
0x08
L1_CONFIG
Layer 1 Configuration
4
0x0C
BIT_RATE_CONFIG
Bit Rate Configuration
page 5-5
0x10
PROT_VER
Protocol Version Control
and Status
6
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