Altera CPRI v6.0 MegaCore Function - Manual (Page 53)

Related Information
Avalon Interface Specifications
For more information about the Avalon-ST protocol, including timing diagrams, refer to the Avalon
Streaming Interfaces chapter.
Direct Vendor Specific Access Interface
If you turn on Enable direct vendor specific access interface in the CPRI v6.0 parameter editor, the
direct vendor specific access interface is available. This interface allows direct access to the Vendor
Specific subchannels in the CPRI hyperframe. The Vendor Specific information is present only in
subchannels 16 through (P-1) of the CPRI hyperframe, where P is the Fast C&M pointer value. Check the
vs_rx_valid
and
vs_tx_ready
signals to ensure you read and write this interface at the time that
corresponds to the correct position in the CPRI frame. If you implement the AUX interface, you can read
the value on the
aux_rx_x
or
aux_tx_x
output signal to identify the current position in the frame.
This interface is Avalon-ST compliant with a read latency value of 1.
You can alter the transmit latency with the Auxiliary latency cycle(s) parameter.
Table 3-7: Direct Vendor Specific Access Interface Signals
All interface signals are clocked by the
cpri_clkout
clock.
Direct Vendor Specific RX Interface
Signal Name Direction Description
vs_rx_valid[3:0]
Output Each asserted bit indicates the corresponding byte on the
current
vs_rx_data
bus is a valid vendor-specific byte.
vs_rx_data[31:0]
Output Vendor-specific word received from the CPRI frame. The
vs_rx_valid
signal indicates which bytes are valid
vendor-specific bytes.
Direct Vendor Specific TX Interface
Signal Name Direction Description
vs_tx_ready[3:0]
Output Each asserted bit indicates the IP core is ready to receive a
vendor-specific byte from the corresponding byte of
vs_
tx_data
on the next clock cycle.
vs_tx_valid[3:0]
Input Write valid for
vs_tx_data
. Assert bit [n] of
vs_tx_valid
to indicate that byte [n] on the
vs_tx_data
bus holds a
valid value in the current clock cycle.
vs_tx_data[31:0]
Input Vendor-specific word to be written to the CPRI frame.
The IP core writes the individual bytes of the current value
on the
vs_tx_data
bus to the CPRI frame based on the
vs_tx_ready
signal from the previous cycle, and the
vs_
tx_valid
signal in the current cycle.
UG-01156
2014.08.18
Direct Vendor Specific Access Interface 3-23
Functional Description Altera Corporation
Send Feedback