Altera CPRI v6.0 MegaCore Function - Manual (Page 55)

Figure 3-17: Direct VS TX Timing Diagram
Expected behavior on the direct VS TX interface of a CPRI v6.0 IP core running at 0.6144 Gbps.
The
aux_tx_x
signal is not part of this interface and is available only if you turn on the AUX interface in
your CPRI v6.0 IP core variation. However, its presence in the timing diagram explains the timing of the
vs_tx_ready
output signal that you use to identify the clock cycles when you can write VS data to the
CPRI frame.
The
aux_tx_x[7:0]
signal (labelled simply
aux_tx_x
) holds the eight-bit index of the basic frame in the
hyperframe, from the perspective of the AUX interface. The subchannel index is the control word index
modulo 64, available in
aux_tx_x[5:0]
if you turn on the AUX interface in your CPRI IP core.
Note that the write latency is one
cpri_clkout
clock cycle in this example.
cpri_clkout
79 80 81 124 125
15 16 17 60 61
0000 1000 0000 0000 1000
X 1000 X X 1000
X (D2)XXX X X (D1)XXX
aux_tx_x
aux_tx_x[5:0]
vs_tx_ready[3:0]
vs_tx_valid[3:0]
vs_tx_data[31:0]
Auxiliary latency cycle(s) == 0
Pointer-P = 60
Related Information
Avalon Interface Specifications
For more information about the Avalon-ST protocol, including timing diagrams, refer to the Avalon
Streaming Interfaces chapter.
Real-Time Vendor Specific Interface
If you turn on Enable real-time vendor specific interface (R-16A) in the CPRI v6.0 parameter editor, the
real-time vendor specific interface is available. This interface allows direct access to the Real Time Vendor
Specific words in the CPRI hyperframe. Check the
rtvs_rx_valid
and
rtvs_tx_ready
signals to ensure
you read and write this interface at the time that corresponds to the correct position in the CPRI frame. If
you implement the AUX interface, you can read the value on the
aux_rx_seq
or
aux_tx_seq
output
signal to identify the current position in the frame.
This option is only available if you specify a CPRI line bit rate of 10.1376 Gbps for your IP core.
This interface is Avalon-ST compliant with a read latency value of 1.
You can alter the transmit write latency with the Auxiliary latency cycle(s) parameter.
UG-01156
2014.08.18
Real-Time Vendor Specific Interface 3-25
Functional Description Altera Corporation
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