Altera CPRI v6.0 MegaCore Function - Manual (Page 31)

Functional Description
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2014.08.18
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The Altera CPRI v6.0 IP core implements Layer 1 of the CPRI V6.0 specification and provides optional
CPRI V6.0 Layer 2 access points through various interfaces.
Interfaces Overview
Figure 3-1: CPRI v6.0 IP Core Interfaces
The IP core assembles the outbound CPRI frame control words and data from all of these interfaces, and
unloads and routes control words and data from the inbound CPRI frame to the appropriate interfaces,
based on configuration and register settings. With parameter settings, you control the presence or absence
of the AUX interface, the L1 control and status interface, and each of the interfaces that provide dedicated
access to specific parts of the CPRI frame. In contrast, the CPRI interface, the transceiver interfaces, and
the software interface to the IP core registers are always implemented.
L1
xcvr_txdataout
Registers
L1
Inband
Slow
C&M
Fast
C&M
Vendor
Specific
L1
Control and Status
Interface
VSS
Interface
Interface
to Reset Controllers
Interface
to TX PLL
Transmitter
xcvr_rxdatain
CPRI Interface (CPRI Link)
Receiver
Multiplexing
Access to
Ctrl_AxC bytes
in CPRI frame
Access to
IQ Data
in CPRI frame
Full access
to
CPRI frame
Real-Time
Vendor
Specific
HDLC
Serial
Ethernet
PCS
Ctrl_AxC
Interface
RTVS
Interface
Direct IQ
Interface
Transceiver
Reconfiguration
Interface
Dedicated access to specific parts of CPRI frame
AUX
Interface
MII Software
Interface
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