Altera CPRI v6.0 MegaCore Function - Manual (Page 28)

Understanding the Testbench
Altera provides a demonstration testbench with the CPRI v6.0 IP core.
If you click Example Design in the CPRI v6.0 parameter editor, the Quartus II software generates the
demonstration testbench. The parameter editor prompts you for the desired location of the testbench.
The testbench is static and does not necessarily match your IP core variation; you can generate it without
generating an IP core. The testbench scripts generate a DUT that matches the testbench, but you must
manually set the appropriate values for the DUT in the parameter editor before you create the demonstra‐
tion testbench.
The testbench performs the following sequence of actions with the static DUT:
1. Enables transmission on the CPRI link by setting the
tx_enable
bit (bit [0]) of the CPRI v6.0 IP core
L1_CONFIG
register at offset 0x8 (and resetting all other fields of the register)>
2. Configures the DUT at the highest possible HDLC bit rate (for CPRI line bit rate 6.144 Gbps), by
setting the
tx_slow_cm_rate
field of the CPRI v6.0
CM_CONFIG
register at offset 0x1C to the value of
3'b110.
3. Reads the
CM_CONFIG
regster to confirm settings.
4. After the DUT and the testbench achieve link synchronization, executes the following transactions:
a. Performs ten write transactions to the AUX Tx interface and confirms the testbench receives them
on the CPRI link.
b. Performs three write transactions to the VS interface and confirms the testbench receives them
from the DUT on the CPRI link.
c. Performs three write transactions to the Ctrl_AxC interface and confirms the testbench receives
them from the DUT on the CPRI link.
d. Performs 50 HDLC transactions and confirms the testbench receives them from the DUT on the
CPRI link.
e. Performs ten write transactions to the MI interface and confirms the testbench receives them from
the DUT on the CPRI link.
f. Calculates the round-trip delay through the IP core.
Running the Testbench
To run the Altera CPRI v6.0 IP core demonstration testbench, follow these steps.
1. In the Quartus II software IP Catalog, select the CPRI v6.0 IP core and click Add.
2. When prompted, you can specify any output file type (HDL). This setting is relevant only for synthesis
and does not impact simulation of the demonstration testbench.
3. In the CPRI v6.0 parameter editor, set the following parameter values:
Table 2-4: CPRI v6.0 IP Core Variation for Demonstration Testbench
The testbench scripts require that you set these values in the CPRI v6.0 parameter editor before you click Example
Design. The scripts generate the DUT but they require that you provide the parameter values.
Parameter Value
Bit rate (Mbit/s) 6144.0
UG-01156
2014.08.18
Understanding the Testbench 2-17
Getting Started with the CPRI v6.0 IP Core Altera Corporation
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