Cpri v6.0 ip core signals, Cpri v6.0 ip core l2 interface, Cpri v6.0 ip core signals -1 – Altera CPRI v6.0 MegaCore Function User Manual
Page 82: Cpri v6.0 ip core l2 interface -1
CPRI v6.0 IP Core Signals
4
2014.08.18
UG-01156
The CPRI v6.0 IP core communicates with the surrounding design through multiple external signals.
Many of the signal interfaces are optional; their presence or absence depends on whether or not you
enable the corresponding interface in the CPRI v6.0 parameter editor.
In the case of the interfaces that provide direct access to all or part of the CPRI frame, write transmit delay
relative to the AUX TX interface synchronization signals depends on the Auxiliary latency cycle(s)
parameter setting.
CPRI v6.0 IP Core L2 Interface
The CPRI v6.0 IP core optionally communicates with an user-provided Ethernet MAC through the
following signals.
Table 4-1: MII Signals
Signal Name
Direction
Interface
mii_rxclk
Input
RX MII signals
These signals are available only if you turn on Enable
IEEE 802.3 100BASE-X 100Mbps MII in the CPRI v6.0
parameter editor.
mii_rxreset
Input
mii_rxdv
Output
mii_rxer
Output
mii_rxd[3:0]
Output
mii_txclk
Input
TX MII signals
These signals are available only if you turn on Enable
IEEE 802.3 100BASE-X 100Mbps MII in the CPRI v6.0
parameter editor.
mii_txreset
Input
mii_txen
Input
mii_txer
Input
mii_txd[3:0]
Input
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