Altera Stratix V Advanced Systems Development Board - Manual (Page 22)

2–12 Chapter 2: Board Components
Configuration, Status, and Setup Elements
Stratix V Advanced Systems Development Board January 2014 Altera Corporation
Reference Manual
Configuration, Status, and Setup Elements
This section describes the board's configuration, status, and setup elements.
Configuration
This section describes the FPGA, flash memory, and MAX V CPLD System Controller
device programming methods that the Stratix V Advanced Systems development
board supports.
The Stratix V Advanced Systems development board supports three configuration
methods:
■ On-Board USB-Blaster II is the default method for configuring the FPGA using the
Quartus II Programmer in JTAG mode with the supplied mini-USB cable.
■ Parallel flash memory download for configuring the FPGAs using stored images
from the flash memory via FPP at either board power-up or by pressing the
program configuration push button (S2).
■ Serial flash memory download for configuring either FPGA at board power-up via
active serial (x4 AS).
■ External USB-Blaster for configuring the FPGA using an external USB-Blaster.
FPGA Programming over On-Board USB-Blaster II
The on-board USB-Blaster II is implemented using a mini-USB type-B connector (J6), a
USB 2.0 PHY device, and an Altera MAX II CPLD EPM570F100 (U77). This allows for
FPGA configuration using a USB cable that connects directly between the USB port on
the board and a USB port on a PC running the Quartus II software. The on-board
USB-Blaster II masters the JTAG chain.
f For more information about the on-board USB-Blaster II, refer to the on-board
USB-Blaster II page of the Altera Wiki website.
USB_CFG14 T15 1.5-V On-board USB Blaster II configuration
USB_CLK H5 2.5-V On-board USB Blaster II clock
Table 2–4. MAX V CPLD System Controller Device Pin-Out (Part 5 of 5)
Schematic Signal Name
MAX V CPLD
Pin Number
I/O
Standard
Description