Altera Stratix V Advanced Systems Development Board - Manual (Page 55)

Chapter 2: Board Components 2–45
Memory
January 2014 Altera Corporation Stratix V Advanced Systems Development Board
Reference Manual
P2 A5 1.5-V SSTL Class I AE33 M18 Address bus
R8 A6 1.5-V SSTL Class I AJ33 B17 Address bus
R2 A7 1.5-V SSTL Class I AF34 B19 Address bus
T8 A8 1.5-V SSTL Class I AD33 H19 Address bus
R3 A9 1.5-V SSTL Class I AN31 C18 Address bus
L7 A10 1.5-V SSTL Class I AR32 N17 Address bus
R7 A11 1.5-V SSTL Class I AP31 E18 Address bus
N7 A12 1.5-V SSTL Class I AN33 M17 Address bus
T3 A13 1.5-V SSTL Class I AM31 A17 Address bus
M2 BA0 1.5-V SSTL Class I AH33 K17 Bank address bus
N8 BA1 1.5-V SSTL Class I AK33 L17 Bank address bus
M3 BA2 1.5-V SSTL Class I AK32 H17 Bank address bus
K3 CASN 1.5-V SSTL Class I AE30 P17 Column address strobe
K9 CKE 1.5-V SSTL Class I AG32 H16 Clock enable
K7 CLK_N
Differential 1.5-V
SSTL Class I
AE32 P18 Differential output clock
J7 CLK_P
Differential 1.5-V
SSTL Class I
AD32 P19 Differential output clock
L2 CSN 1.5-V SSTL Class I AF32 R19 Chip select
E7 DM0 1.5-V SSTL Class I BC31 F22 Data write mask
D3 DM1 1.5-V SSTL Class I AK24 L21 Data write mask
E7 DM2 1.5-V SSTL Class I AN30 V19 Data write mask
D3 DM3 1.5-V SSTL Class I AG29 W18 Data write mask
E7 DM4 1.5-V SSTL Class I AV29 H14 Data write mask
D3 DM5 1.5-V SSTL Class I AV32 P16 Data write mask
E7 DM6 1.5-V SSTL Class I AV26 U15 Data write mask
D3 DM7 1.5-V SSTL Class I BA27 C13 Data write mask
E3 DQ0 1.5-V SSTL Class I AW30 A20 Data bus
F7 DQ1 1.5-V SSTL Class I BB30 C21 Data bus
F2 DQ2 1.5-V SSTL Class I BD31 B20 Data bus
F8 DQ3 1.5-V SSTL Class I BC32 E20 Data bus
H3 DQ4 1.5-V SSTL Class I BB32 B22 Data bus
H8 DQ5 1.5-V SSTL Class I AY31 F21 Data bus
G2 DQ6 1.5-V SSTL Class I BD32 A22 Data bus
H7 DQ7 1.5-V SSTL Class I BA30 E21 Data bus
D7 DQ8 1.5-V SSTL Class I AH24 F20 Data bus
C3 DQ9 1.5-V SSTL Class I AJ24 J21 Data bus
C8 DQ10 1.5-V SSTL Class I AH28 G20 Data bus
C2 DQ11 1.5-V SSTL Class I AK26 J22 Data bus
Table 2–23. FPGA1 DDR3 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 7)
Board
Reference
Schematic
Signal Name
I/O Standard Stratix V GX FPGA1 Device Pin Number Description