Altera Stratix V Advanced Systems Development Board - Manual (Page 49)

Chapter 2: Board Components 2–39
Components and Interfaces
January 2014 Altera Corporation Stratix V Advanced Systems Development Board
Reference Manual
32 HSMC_RX_N0 1.4-V PCML AB44 Transceiver receive channel
26 HSMC_RX_P1 1.4-V PCML Y43 Transceiver receive channel
28 HSMC_RX_N1 1.4-V PCML Y44 Transceiver receive channel
22 HSMC_RX_P2 1.4-V PCML V43 Transceiver receive channel
24 HSMC_RX_N2 1.4-V PCML V44 Transceiver receive channel
18 HSMC_RX_P3 1.4-V PCML T43 Transceiver receive channel
20 HSMC_RX_N3 1.4-V PCML T44 Transceiver receive channel
14 HSMC_RX_P4 1.4-V PCML M43 Transceiver receive channel
16 HSMC_RX_N4 1.4-V PCML M44 Transceiver receive channel
10 HSMC_RX_P5 1.4-V PCML K43 Transceiver receive channel
12 HSMC_RX_N5 1.4-V PCML K44 Transceiver receive channel
6 HSMC_RX_P6 1.4-V PCML H43 Transceiver receive channel
8 HSMC_RX_N6 1.4-V PCML H44 Transceiver receive channel
2 HSMC_RX_P7 1.4-V PCML F43 Transceiver receive channel
4 HSMC_RX_N7 1.4-V PCML F44 Transceiver receive channel
29 HSMC_TX_P0 1.4-V PCML W41 Transceiver transmit channel
31 HSMC_TX_N0 1.4-V PCML W42 Transceiver transmit channel
25 HSMC_TX_P1 1.4-V PCML U41 Transceiver transmit channel
27 HSMC_TX_N1 1.4-V PCML U42 Transceiver transmit channel
21 HSMC_TX_P2 1.4-V PCML R41 Transceiver transmit channel
23 HSMC_TX_N2 1.4-V PCML R42 Transceiver transmit channel
17 HSMC_TX_P3 1.4-V PCML N41 Transceiver transmit channel
19 HSMC_TX_N3 1.4-V PCML N42 Transceiver transmit channel
13 HSMC_TX_P4 1.4-V PCML J41 Transceiver transmit channel
15 HSMC_TX_N4 1.4-V PCML J42 Transceiver transmit channel
9 HSMC_TX_P5 1.4-V PCML K39 Transceiver transmit channel
11 HSMC_TX_N5 1.4-V PCML K40 Transceiver transmit channel
5 HSMC_TX_P6 1.4-V PCML H39 Transceiver transmit channel
7 HSMC_TX_N6 1.4-V PCML H40 Transceiver transmit channel
1 HSMC_TX_P7 1.4-V PCML G41 Transceiver transmit channel
3 HSMC_TX_N7 1.4-V PCML G42 Transceiver transmit channel
41 HSMC_D0 2.5-V BB9 Dedicated CMOS I/O bit 0
42 HSMC_D1 2.5-V AN37 Dedicated CMOS I/O bit 1
43 HSMC_D2 2.5-V AT11 Dedicated CMOS I/O bit 2
44 HSMC_D3 2.5-V BD8 Dedicated CMOS I/O bit 3
35 JTAG_TCK 2.5-V AL34 JTAG clock
38 JTAG_FPGA2_TDO 2.5-V AL36 JTAG data input
37 HSMC_JTAG_TDO 2.5-V — JTAG data output
Table 2–22. HSMC Port Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)
Board
Reference
(J1)
Schematic Signal Name I/O Standard
Stratix V GX
FPGA2 Device Pin
Number
Description